Conventionally, the subrange ADC includes two flash ADCs. FIG. 1 shows a schematic diagram of a conventional subrange ADC. In FIG. 1, the subrange ADC receives an input voltage Vin and includes a X-bit flash coarse ADC, a resistor ladder, a Y-bit flash fine ADC, a switching network and an encoder for generating a digital code having (X+Y) bits corresponding to an input voltage Vin. FIG. 2 is a 6-bit embodiment of the conventional subrange ADC as shown in FIG. 1, and the subrange ADC receives a reference voltage Vref and an input voltage Vin, generates the corresponding digital code Dout and includes an encoder, two comparator arrays, a plurality of switches and two buffers, each of which has a gain of 1. As for the configuration of the conventional subrange ADC, if the resolution of the coarse ADC is X bits, and the resolution of the fine ADC is Y bits, then the fine ADC requires a reference switching network to set the reference voltages required by the fine ADC. Comparing with the flash ADC, the subrange ADC requires a less number of comparators, but the subrange ADC requires a longer conversion time. Also, complex switching network results in high technical difficulty in designing high-speed and high-resolution subrange ADCs. Therefore, a subrange ADC with this kind of combination can seldom have a resolution higher than 8. Besides, a SAR ADC could achieve a high energy efficiency of analog-digital conversion, but the SAR ADC has to go through many cycles to finish a data conversion, and thus the operation speed is limited. In short, the SAR ADC has the characteristics of low power consumption, and the flash ADC has the advantage of high operational speed. To combine the flash ADC with the SAR ADC properly, a subrange ADC having high speed and low power consumption can be realized. FIG. 3 shows a schematic diagram of a subrange ADC comprising a flash ADC and a SAR ADC. As shown in FIG. 3, the subrange ADC is designed by intuition. In FIG. 3, the subrange ADC receives an input voltage Vin, and includes a X-bit flash coarse ADC, a resistor ladder, a Y-bit SAR fine ADC, a switching network and an encoder for generating a digital code having (X+Y) bits corresponding to an input signal (for generating the input voltage Vin). FIG. 4 is a 6-bit embodiment of the subrange ADC as shown in FIG. 3, the SAR ADC receives an input voltage Vin and a reference voltage Vref, generates the corresponding digital code Dout and includes a comparator array, a reference voltage generating circuit, a plurality of switches, a capacitor array receiving references voltages Vrefp and Vrefn, a comparator, a SAR logic and an encoder. However, the resistance value of the resistor ladder in the flash ADC is not allowed to be too small for the reason of low power consumption. Accordingly, the capacitor array driving the SAR ADC through the reference switching network has an RC time constant value usually not small, which will cause the settling speed of the reference voltage to be quite slow during this procedure, and the required conversion time is thus prolonged.
Generally speaking, the binary weighted capacitor array has a better linearity than the split capacitor array or the C-2C capacitor array so as to avoid the complex digital correction. But a drawback of the binary weighted capacitor array is that the capacitance value of its maximum bit is a sum of all the remaining bits. That means, to add a bit, the total capacitance value of the whole capacitor array will become doubled. When a high resolution version is designed, an overly large input capacitance value will limit the input bandwidth and result in that the capacitor switching requires even larger energy consumption. For a SAR ADC, after a comparison is ended and before the next comparison begins, the voltage value of the DAC in the SAR ADC must be confirmed to be settled enough to reach the required accuracy. During the whole conversion procedure, the capacitor having the maximum weight in the capacitor array (being one half of the whole capacitance value in the capacitor array) requires the longest settling time, and it is the main bottleneck of the operational speed of the SAR ADC. If the flash ADC is employed to speed up the first several capacitors with the maximum weights, then the whole subrange ADC only requires going through a large voltage variation once. As for the operations thererafter, since the capacitance of the capacitor with the maximum weight in the fine SAR ADC is significantly reduced, the settling time required is relatively shortened so as to have the advantages in speed.
Therefore, it is the intention of the present invention to combine the flash ADC with the SAR ADC so as to draw on the strong points to offset the weaknesses and to have the advantages of both the flash ADC and the SAR ADC.
Keeping the drawbacks of the prior arts in mind, and employing experiments and research full-heartily and persistently, the applicant finally conceived a subrange analog-to-digital converter and a method thereof.